The semiconductor industry continually strives to increase device performance and device density by reducing device dimensions. For a given chip size, device density can be increased by reducing the lateral distance separating active devices, or the device isolation width. The desire to reduce device isolation width, while maintaining the necessary electrical isolation between adjacent active devices, has led to the development of several different isolation schemes.
One technique which as been proposed for device isolation in high density integrated circuits is trench isolation. With trench isolation, field oxide encroachment of the surrounding active regions is eliminated, and therefore device isolation width can be reduced. Unfortunately, integrated circuits fabricated with existing trench isolation schemes often suffer from premature gate oxide breakdown, and thus have poor reliability. One reason for the premature breakdown is that gate oxide grown near the trench corner has a lower breakdown voltage as compared to that grown in other areas. This is because near the trench corner the silicon substrate oxidizes at a slower rate during gate oxidation, and this results in the gate oxide being thinner near the trench corner, as compared to that grown in other areas. In addition, due to the abrupt profile of the trench corner, high electric fields are generated near the trench edge during device operation, and these high electric fields further degrade the breakdown voltage of the thinned gate oxide. Accordingly, a need exists for a trench isolation structure that allows high density integrated circuits to be fabricated with improved reliability.